Cadence to Augment RC Extraction through New Quantus QRC Extraction Solution

Bangalore: The leader in global electronic design innovation, Cadence Design Systems, Inc. (NASDAQ: CDNS) has introduced Cadence Quantus QRC Extraction Solution as a next-generation tool for RC extraction. The new device is engineered to design signoff and to accelerate its performance by delivering faster runtime for single and multi-corner extraction versus competing solutions.

The 1988 born, American electronic design automation (EDA) software and engineering services company, Cadence is known for its growing portfolio of design IP and verification IP for memories, interface protocols, analog or mixed-signal components and specialized processors design the transistors, standard cells, and IP blocks that make up SoCs. The company has a current market cap of $5.01 billion and has built a strong portfolio across globe. The new product of this brand is set-up to hold up both system-on-chip (SoC) and custom or analog designs.

Cadence’s Quantus QRC Extraction Solution boosts up the high-accuracy modeling engine from the previous model of QRC Extraction product. This ensures foundry certified libraries ‘qrctechfiles’ for existing users. The next-generation solution comes with comprehensive potential to support FinFET features. Enhanced in both Encounter and Virtuoso platforms, the new tool is claimed to have the tightest correlation to foundry golden data at TSMC versus competing solutions.

“After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy. Quantus QRC Extraction Solution’s ability to perform multi-corner extraction in a single run using foundry-certified accuracy enables notable design implementation time improvements. This is a well integrated solution that complements Cadence’s existing Encounter Digital Implementation tool,” says Sumbal Rafiq, Director of Engineering, AppliedMicro.

“Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools,” says Radhakrishnan Pasirajan, Vice President, Silicon Engineering, Open-Silicon. “As a company that consistently achieves first-pass silicon success, Open-Silicon relies on the massive parallelism and accuracy of this tool to achieve significant performance improvement in its designs. Its scaling capability to utilize hundreds of CPUs, allows our designers to quickly navigate through signoff extraction bottlenecks during tapeout”.

“Our customers have emphasized that it is imperative for a signoff parasitic extraction tool to provide the highest accuracy with the fastest turnaround time to ensure timely design closure,” says Anirudh Devgan, Senior Vice President, Digital & Signoff Group, Cadence. “Quantus QRC Extraction Solution has been proven to provide best-in-class accuracy for FinFET designs and deliver significantly better performance versus competing solutions”.